The transmitter activates its high-speed current driver, setting the lines to differential zero.
The transition between Low-Power and High-Speed modes follows a strictly defined hardware state machine sequence called the and High-Speed Entry/Exit protocols. High-Speed Data Burst Entry Sequence
To initiate a high-speed data transmission burst, the lane transitions from its default Low-Power Idle state ( LP-11 ) through a series of step-down sequences: Both DPcap D sub cap P DNcap D sub cap N lines are driven high (1.2V). LP-01: The DNcap D sub cap N line is driven low while DPcap D sub cap P remains high. LP-00: The DPcap D sub cap P line is also driven low. This marks the Bridge phase. mipi d phy 20 specification top
| Feature | High-Speed (HS) Mode | Low-Power (LP) Mode | | :--- | :--- | :--- | | | Bulk data transfer (image/video) | Control commands and low-speed data | | Signal Type | Differential (LVDS) | Single-ended (LVCMOS) | | Typical Data Rate | 80 Mbps to 4.5+ Gbps | ≤ 10 Mbps | | Termination | Terminated (100Ω) | Non-terminated | | Power Consumption | Higher (for high throughput) | Ultra-low (as low as 0.1mW per channel) |
: The specification is designed to be backward compatible with previous D-PHY versions, allowing for easier integration with existing MIPI CSI-2 and DSI-2 protocols. Target Applications LP-01: The DNcap D sub cap N line
It supports high-speed idle modes, reducing power draw during brief breaks in transmission. 4. Fast Lane Turnaround (BTA)
For engineers designing PCB layouts, the "MIPI D-PHY 2.0 specification top" electrical parameters are critical. | Feature | High-Speed (HS) Mode | Low-Power
D-PHY v2.0 remains the dominant topology for mainstream mobile sensors due to its simpler logic controller and lower latency for short bursts.
It includes optimized low-power states (ALP) for when high bandwidth is not required.